FIG. 10 shows an electrical construction of a breakdown detecting circuit for detecting a breakdown around a load in a driving circuit, which is disclosed in JP-A-2000-293201 (hereafter “Patent Document 1”). As a load is assumed a switched reluctance motor for driving a linear solenoid constituting the transmission of a vehicle, for example. The switched reluctance motor is disposed in a circuit for driving one-phase (W-phase) in a three-phase winding wire. A power-source side current mirror circuit 1, an L load 2 which is a winding wire of a motor and a ground-side current mirror circuit 3 are connected in series between the power source and the ground. The current mirror circuit 1 is constructed by two N-channel FETs 1a and 1b, and the current mirror circuit 3 is constructed by two N-channel FETs 3a and 3b. 
An inverse-direction diode 4 is connected between the power source and the ground side terminal of the L load 2, and a diode 5 in the opposite is connected between the L load 2 and the power source side terminal. A control circuit 6 outputs gate signals to the FETs 1a, 1b of the current mirror circuit 1 and the FETs 3a, 3b of the current mirror circuit 3 to switch these FETs. The FETs are disposed at the power source side and the ground side to supply current to the L load as described above in consideration of fail safe when any one of the FETs is short-circuited.
Resistors 7 and 8 are connected between the source of the FET 1b and the L load 2 and between the source of FET 3b and the ground, and voltage amplifiers 9 and 10 are connected between both the respective ends of the resistors 7 an 8, respectively. The output signals of the voltage amplifiers 9 and 10 are supplied to an L breakdown detecting circuit 11, and the L breakdown detecting circuit 11 refers to and compares the output signals of the voltage amplifiers 9 and 10 at the output timings of the gate signals of the FETs 1a, 1b and the FETs 3a, 3b under the control of the control circuit 6 to detect a breakdown such as incomplete short-circuit occurring in the L load 2 or the like. Circuits having the same construction are disposed with respect to the other U, V phases.
However, in the technique disclosed in the patent document 1, current flowing in the L load 2 is converted to a voltage by the resistors 7 and 8, and thus a conversion error occurs. Furthermore, the terminal voltage of the resistor is reduced in a low current region, and thus there is a problem that dispersion is liable to occur in detection precision.